The present invention relates generally to a double positive-feedback-loop precharge CMOS single-ended sense amplifier, and more particularly to a double positive-feedback-loop precharge CMOS single-ended sense amplifier that eliminates the leakage current problem and reduces the space required due to the clock signal and by the complexity of the design respectively.
Most dynamic RAMs and Static RAMs use differential sense amplifiers having good common mode noise rejection ratios. A single-ended differential sense amplifier is employed to fit the single-ended bit-line structure. Especially in multiprocessing and super scalar CPU structure, multiport memories are used for space considerations. The importance of the single-ended sense amplifier will increase as its applications grow.
FIG. 1 is a circuit diagram of a conventionally designed static sense amplifier including two NMOS transistors 10 & 12, a capacitor 14, and two inverters 16 & 18. The inverter 16 consist of a PMOS 162 and a NMOS 164. Inverter 18 consists of a PMOS 182 and an NMOS 184. When input signal V.sub.in is a logic LOW, NMOS 10 is cut off and NMOS 12 pulls up the voltage potential of node A until it reaches a particular level. At this point, both PMOS 162 and NMOS 164 in inverter 16 are on. Meanwhile the voltage potential at node B is between V.sub.dd and V.sub.ss. Because of the negative feedback circuit path, NMOS 12 can not fully charge node A to the level of V.sub.dd. Later, when input signal. V.sub.in is a logic HIGH, NMOS 10 is on and discharges node A until the voltage of node A drops slightly below the threshold voltage of inverter 16. At the same time, NMOS 12 is turned on by NMOS 10. In this case, NMOS 10 and NMOS 12 form a voltage divider that clamps the potential of node A between 0 volt (Vss) and the threshold voltage of inverter 16. As a result, the potential of node A is not charged and discharged between Vss and Vdd; instead it is confined around the threshold voltage of inverter 16.
However, when input signal V.sub.in is a logic LOW (i.e., NMOS 10 is cutoff), PMOS 162 and NMOS 164 of inverter 16 are both on; and as a result, a direct current path is formed. Likewise, when input signal V.sub.in is a logic HIGH (i.e., NMOS 10 is on), NMOS 10 and NMOS 12 are both on and form a direct current path. The direct current path wastes electric energy. Therefore, the above method of prior art is energy consuming.
FIG. 2 is a circuit diagram of a conventional threshold voltage sense amplifier which includes: a NOR gate 20; three PMOS transistors 21,24,25; two NMOS transistors 22,26; a capacitor 23; and an inverter 27. The symbols ".phi..sub.1 " and ".phi..sub.2 " are phase 1 and phase 2 of a nonoverlapped two-phase clock signal. Phase 1 is the pre-charge phase and phase 2 is the evaluation phase. In phase 1, node D is pre-charged to V.sub.dd, and node E is pre-discharged to V.sub.ss. In phase 2, if the input signal V.sub.in is low, then node C is pulled high, and both node D and node E drop to low. If V.sub.in is high, then node D remains high, and V.sub.out is also high. But if V.sub.in is high, node D may not contain enough charges to stay high. In other words, the current leakage of NMOS 22 may be so large that node D drops to a value smaller than V.sub.dd in the evaluation phase. The error occurs when the value of node D is less than V.sub.dd -.vertline.V.sub.TP .vertline..
Another drawback of a conventional threshold voltage sense amplifier is its use of memory space. The NOR gate and the NMOS transistors have to be duplicated many times in a memory layout, since every memory cell is connected to a sense amplifier through these elements.